1. Field of the Invention
This invention relates to electronic test systems. Specifically, the present invention relates to configurable electronic test systems.
2. Description of the Related Art
Modern electronics systems have become more complex. As a result, the systems used to test modern electronic systems have also become more complex. Conventional digital electronics are deployed in printed circuit boards (PCB) or integrated circuits. These printed circuit boards and integrated circuits include millions of digital components such as logical gates, memories such as latch arrays, etc. In addition, the electronic systems include millions of connections between the components to communicate signals. The connection between two components is referred to as a trace.
Test systems are used to test conventional printed circuit boards and integrated circuits. These test systems typically include an interface, known as a fixture, for interfacing with a device under test (DUT). In addition, test patterns and electrical signals are generated by tester electronics, which connected to the fixture. The DUT typically sits on top of the fixture and the fixture typically sits on top of the tester electronics.
Conventional test systems typically are characterized as wired test systems or wireless test systems. In a wired test system a number of interface boards are loaded in the fixture. One specific interface board known as a probe plate includes a pattern of holes for holding a number of probes. The probes provide an electrical pathway from the tester electronics, through the fixture, to the DUT. When the probes are placed in the holes the probes form a pattern known as a probe field. The probe field makes contact with the DUT on one side of the probes to create an electrical contact point between the probe and the DUT. The probe field is specific to the DUT. In a wired test system, wires are wrapped on the other end of the probes and are run to the tester electronics. In this way an electrical pathway is established between the tester electronics, across the wires, to the probes and then to the DUT.
In a wireless test system, in addition to the probe plate, an interface board populated with traces is placed in the fixture. The interface board is known as a wireless PCB. The topside of the wireless PCB is placed in contact with the end of the probes that were previously connected to the wires in the wired test system. A second set of probes then make contact with the underside of the wireless PCB on one end and with interface contacts in the electronic tester at the other end. As a result, an electrical pathway is once again established from the tester electronics, through the fixture, to the DUT. The first leg of the electronic pathway runs from interface points on the tester electronics, to the probes and to the underside of the wireless PCB. Current may then run across traces in the wireless PCB. In the second leg of the electronic pathway, the probes which contact the top-side of the wireless PCB extend upward in the fixture and make contact with the underside of the DUT.
The tester electronics include a mixture of hardware and software directed at generating test patterns, which will be transmitted through the fixture to the DUT. A reverse path is also established back to the tester electronics to receive the test pattern and determine whether the DUT passed or failed the test. Different types of software may be implemented when a tester is implemented. The software is implemented to operate with the hardware and configure the type of test that should be implemented. The software hardware configuration is static and typically does not accommodate changes in test patterns or sequences.
A class of conventional test electronics have developed known as automatic test equipment (ATE). An ATE is a mixture of software and hardware capable of automatically running testing sequences on a DUT. Controlled by software routines, an ATE may perform sophisticated pattern generation and analysis of returning test patterns. In addition, an ATE may make adjustments and alter testing based on the return test patterns.
An example of a common test used in conventional test systems (e.g. ATE) is a boundary-scan test. A boundary-scan may be used to find simple manufacturing faults such as an xe2x80x9copenxe2x80x9d on a DUT. To perform a full test on a DUT all devices pins must be tested. On a complex DUT this may create a significant hurdle since first the DUT must be thoroughly understood. In addition a specific test must be constructed and then debugged. For complex DUT""s this may take weeks or months. A Boundary-scan provides a method to exercise pins on the DUT with a limited amount of effort.
In order to perform a boundary scan, circuitry is added to the standard logic function of the DUT. At a minimum this includes hardware known as a Test Access Port to control the boundary-scan operation. The test access receives a test clock (TCK) for providing timing information through the test access port and a test mode select (TMS) for selecting a test mode of operation. In addition, contact points known as boundary scan cells are connected to the DUT. Some of the boundary scan cells known as test data in (TDI) cells, are used to apply test patterns to the DUT. Other boundary scan cells known as test data out (TDO) cells are used to read out test patterns applied to the DUT. In addition, 4 or 5 extra control pins are also added to the DUT to control the boundary scan function.
The most basic boundary scan test is an external test. An external test verifies that the DUT input/output drivers are functional, the bond wires are intact and the digital components are properly soldered to the board. In an external test, data is scanned into the device serially through the TDI line, clocked around the boundary-scan cell chain and then applied to the outputs. The results are sampled by the ATE. Patterns are applied to the inputs of the DUT, captured by the input boundary cells and clocked out the TDO line. The results are sampled by the ATE. Past data has shown that if a DUT passes the external test, there is a high probability the DUT will function properly.
An internal test can be used to test the core logic of the DUT. The internal test has two parts. During the first part of the internal test a sequence of instructions are activated. An internal self-test is performed and after a prescribed number of clock cycles, the results are scanned out the TDO for verification. In the second part of the internal test instructions are performed which provide the means to shift static test patterns into the device through the boundary scan chain, apply to the static test patterns to the core logic and shift out the resultant pattern through the TDO for analysis by the ATE.
Boundary-scan testing may be applied to technologies (e.g. DUTs) that have multiple chip modules. In conventional devices, multiple chip modules may be connected in a chain. These multiple chip modules typically fall into two categories. The first category are Multi-chain modules that have access to an internal node and the second category are multi-chain modules that don""t have access to internal nodes.
When there is internal node access, boundary scan cells may be connected around the perimeter of the multi-chain modules. In addition, boundary scan cells may be positioned on an internal interface of each multi-chain module. In this configuration, patterns may be scanned in serially (e.g. TDI) to the boundary cells on the perimeter of a first module in the multi-chain module and applied in parallel to internal boundary cells located between the first module and a second module. These patterns are then captured from boundary scan cells located on the perimeter of the second module in the chain and scanned out serially (e.g. TDO). As a result, connections internal to the board become controllable or visible through the boundary-scan.
Some conventional ATE systems provide the means to test a multi-chain module that include conventional logic (e.g. non-boundary-scan parts). In this scenario, patterns are scanned in serially through the appropriate boundary scan device and applied in parallel to the conventional logic. The output states are captured by other boundary scan devices, scanned out serially and verified by the ATE.
Conventional test systems are designed to accommodate a specific DUT. A fixture is designed to accommodate a specific DUT and the ATE is developed to test a specific DUT. For example, supposed that an ATE is configured to perform a boundary-scan on a multi-module chain. In addition, suppose one of the modules is connected into the chain after the initial configuration of the ATE. The additional module breaks the boundary-scan test into the testing of two chain segments. Each of which has to be tested separately.
As a result of the addition of the last module in the chain, three interconnections are formed from the perspective of the boundary scan test. Connections that occur between parts of the first chain segment, connections between parts of the second chain segment and interconnections between the first and the second chain segment. As a result, the ATE is forced to build three test suites, analyze the results of the three test suites and integrate the results in a format that is suitable for an end-user.
However, all of the test routes, the placement of the DUT and the design of the fixture that interfaces with the DUT are static. For example, a specific fixture has to be developed to test a multi-chain module with two modules. If a third module is added a new fixture configuration must be implemented to accommodate and test a multi-chain module with multiple modules. This often requires a new placement of probes, new probe plates and new test patterns generated from the tester electronics. In other words, this may require a significant design effort on the part of the testing engineer. For example, a new probe plate may have to be designed and developed. New software code may have to be developed to accommodate the new module that is added to the end of the chain.
In addition to the problems associated with performing test when the DUT configuration changes, there are also changes that may have to be made to accommodate different test. For example, short detection test, powered open detection test and connectivity verification test are all different types of test that may require reconfiguration of the tester including new or different software testing code or routines. Performing the various reconfigurations and redesigns are time-consuming and cost the designer and ultimately the end-user.
Thus there is a need in the art for a test system that can accommodate different DUT testing scenarios. There is a need in the art for an easy way to generate testing sequences for a changing DUT. Lastly, there is a need in the art for a fixture technology that will integrate with a tester capable of changing test sequences based on changes to the DUT.
A re-configurable test system is presented. The test system includes an adapter assembly capable of engaging different contact points in a device under test. The test system also includes a tester assembly, which interfaces with the adapter assembly. The tester assembly includes configurable logic units, which are used to generate test signals to the different points of contact on the device under test.
In one embodiment of the present invention, a system comprises an adapter assembly comprising, a first probe plate capable of holding a probe in a first position and in a second position. A second probe plate positioned below the first probe plate, the second probe plate capable of holding the probe in the first position and in the second position and an electronics assembly interfacing with the adapter assembly. The electronics assembly comprising a printed circuit board having a topside and an underside. A first pad coupled on the topside of the printed circuit board, the first pad positioned to make contact with the probe in the first position. A second pad coupled on the topside of the printed circuit board, the second pad positioned to make contact with the probe in the second position. A first configurable logic unit coupled to the underside of the printed circuit board, the first configurable logic unit generating signals through the printed circuit board to the first pad, when the probe is in the first position and a second configurable logic unit coupled to the underside of the printed circuit board, the second configurable logic unit generating signals through the printed circuit board to the second pad when the probe is in the second position.
A system comprises an adapter assembly housing a plurality of probes capable of deflecting from a first position to a second position; and an electronics assembly interfacing with the adapter assembly, the electronics assembly comprising a plurality of configurable logic units, each of the plurality configurable logic units capable of generating a variety of test patterns for interfacing with the plurality of probes when the plurality of probes are in the first position and when the plurality of probes are in the second position.
An assembly comprises a first probe plate including a first hole extending through the first probe plate, the first hole extending through the first probe plate including a first flange area accommodating deflection of a probe; and a second probe positioned below the first probe plate, the second probe plate including a second hole extending through the second probe plate, the second hole extending through the second probe plate including a second flange area accommodating deflection of the probe, the second hole extending through the second probe plate aligning with the first hole aligning through the first probe plate; and a probe positioned in the first hole extending though the first probe plate and positioned in the second hole extending through the second probe plate, the probe capable of lateral movement by deflecting within the first flange area accommodating deflection of the probe and deflecting within the second flange area accommodating deflection of the probe.
An assembly comprises a printed circuit board having a topside and an underside; a first pad coupled to the topside of the printed circuit board, the first pad positioned to make contact with a probe in a first position; a second pad coupled to the topside of the printed circuit board, the second pad positioned to make contact with the probe in a second position; and a configurable logic unit coupled to the underside of the printed circuit board, the configurable logic unit generating signals through the printed circuit board to the first pad, when the probe is in the first position and generating signals through the printed circuit board to the second pad when the probe is in the second position.
An apparatus comprises a printed circuit board including a pad; a power source applying source voltage to the pad; a reference input carrying a reference voltage; and a comparator coupled to the power source and coupled to the reference input, the comparator generating an output in response to the source voltage and in response to the reference voltage.